00647nam a2200193Ia 4500008004100000020001800041082001700059100002100076245006300097250000700160260004100167300002300208500001900231600002700250650001500277942000700292952013700299999001700436240925s9999    xx            000 0 und d  a9788131501955  a621.3815 UYE  aUyemura, John P. 0aChip Design for Submicron VLSI: cmos layout and simulation  aNA  aAustralia:bCENGAGE Learningc,2013.  a640p.b0fOriginal  aIncludes Index  aEngineering Technology  aTechnology  cBK  001040708ETaUITUbUITUd2015-01-26eParamount Book Pvt Ltdg500.00l0o621.3815 UYEpQ10036r2024-09-25 07:15:34w2024-09-25yBK  c12535d12535