000 00519nam a2200181Ia 4500
008 240925s9999 xx 000 0 und d
020 _a9788177589184
082 _a621.395 PAL
100 _aPalnitkar, Samir
245 0 _aVerilog HDL A Guide to Digital Design and Synthesis IEEE 13-2001 Compliant
250 _a2nd
260 _aNew Delhi:
_bPearson Education
_c,2013.
300 _axxi,678p.
_b0
_fOriginal
500 _aIncludes Index
600 _aElectrical Engineering
650 _aTechnology
942 _cBK
999 _c13222
_d13222