| 000 | 00482nam a2200181Ia 4500 | ||
|---|---|---|---|
| 008 | 240925s9999 xx 000 0 und d | ||
| 020 | _a9788126519316 | ||
| 082 | _a621.392 PAD | ||
| 100 | _aPadmanabhan, T. R.; Sundari, B. Bala Tripura | ||
| 245 | 0 | _aDesign Through Verilog HDL | |
| 250 | _aNA | ||
| 260 |
_aNew Delhi: _bWiley _c,2015. |
||
| 300 |
_a642p. _b0 _fOriginal |
||
| 500 | _aIncludes Index | ||
| 600 | _aEngineering Technology | ||
| 650 | _aTechnology | ||
| 942 | _cBK | ||
| 999 |
_c13935 _d13935 |
||