000 00526nam a2200181Ia 4500
008 240925s9999 xx 000 0 und d
020 _a9788177589184
082 _a621.392 PAL
100 _aPalnitkar, Samir
245 0 _aVerilog HDL: a guide to digital design and synthesis IEEE 1364-2001 compliant
250 _a2nd
260 _aUttar Pradesh:
_bPearson Education Inc
_c,2018.
300 _a717p.
_b0
_fOriginal
500 _aIncludes Index
600 _aEngineering Technology
650 _aTechnology
942 _cBK
999 _c17520
_d17520